Answer to Question #241646 in Electrical Engineering for KUSHAL

Question

Design a circuit that would be able to shift bits but also store them for a duration of time. 

Answer 1

--VHDL synthesis

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity shft is

port( W:in std_logic_vector(3 downto 0);

     Y:out std_logic_vector(3 downto 0);

     S:in std_logic_vector(1 downto 0));

     

end shft;

architecture Behavioral of shft is

begin

process(S,W)

begin

case S is

when "01" =>

Y(3)<=W(0);

Y(2)<=W(3);

Y(1)<=W(2);

Y(0)<=W(1);

when "10" =>

Y(3)<=W(1);

Y(2)<=W(0);

Y(1)<=W(3);

Y(0)<=W(2);

when "11" =>

Y(3)<=W(2);

Y(2)<=W(1);

Y(1)<=W(0);

Y(0)<=W(3);

when others =>

Y<=W;

end case;

end process;

end Behavioral;

----------------------

--VHDL test bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY shft_tb IS

END shft_tb;

ARCHITECTURE behavior OF shft_tb IS

  

COMPONENT shft

PORT(

W : IN std_logic_vector(3 downto 0);

Y : OUT std_logic_vector(3 downto 0);

S : IN std_logic_vector(1 downto 0)

);

END COMPONENT;

  

--Inputs

signal W : std_logic_vector(3 downto 0) := (others => '0');

signal S : std_logic_vector(1 downto 0) := (others => '0');

   --Outputs

signal Y : std_logic_vector(3 downto 0);

BEGIN

  -- Instantiate the Unit Under Test (UUT)

uut: shft PORT MAP (

W => W,

Y => Y,

S => S

);

  

-- Stimulus process

stim_proc: process

begin     

-- hold reset state for 100 ns.

wait for 100 ns;  

W<="1011";

     wait for 10 ns;

     S<="01";

     wait for 10 ns;

     S<="10";

     wait for 10 ns;

     S<="11";

     

  

wait;

end process;

END;

---------------------------

-- test bench results