Answer to Question #241645 in Electrical Engineering for Amn

Question

The outputs of four registers, A, B, C, D, H, L are connected through 8:1 line
multiplexer to the input of a fifth register, X. Each register is 16 bits long. The
required transfers are dictated by four timing variables, T0 through T3 as follows:
T0 : X←A
T1 : X←B
T2 : X←C
T3 : X←D
The timing variables are mutually exclusive, which means that only one variable is
equal to 1 at any given time, while the others are equal to 0. Draw a block diagram
showing the hardware implementation of the register transfers. Include the
connections necessary from the four timing variables to the selection inputs of the
multiplexers and to the load input of register X.

Answer 1

Notably, we see that output 1 of register A is connected to input 0 of MUX 1 because this input is labeled A1 . The diagram shows that the bits in the same significant position in each register are connected to the data inputs of one multiplexer to form one line of the bus. Thus, MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the registers, and similarly for the other two bits.

This design connection can be shown as captured below: