Answer to Question #21747 in Programming & Computer Science for Sam

Question

I have a computer architecture assignment due 2 days from now. It includes writing a vhdl code involving a single-precision FP adder. The file should contain FP adder entity and FP adder structural architecture. The structural architecture should contain one component for each pipeline stage of your design, including the pipeline stage output
register.
For example, you could implement each of the 5 steps in the FP adder design from the class slides as a separate pipeline stage. Recall that these steps include:
1. Compare exponents
2. Shift smaller number right
3. Add
4. Normalize
5. Round
In this design, it takes 5 cycles from start to finish to complete one FP add. However, there could be 5 different FP adds processed in parallel, one different add in each of the 5 pipeline stages above. This means that even though it takes 5 cycles to complete one add, the design could produce one FP add result every cycle.

How much will it cost to get this assignment done on the 10th of january?please get back to me asap

Answer 1

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