Describe how pipelining normally speeds up the processing done by a computer
The inner functions of the processor can be broken down into Fetch-Decode-Execute. But, not all parts of the processor are simultaneously involved in the command processing/execution in the non-pipelined processor. To make pipelining possible, the following steps were introduced for the reduced instruction set computer central processing units (RISC CPUs):
1. Instruction fetch
2. Instruction decode and register fetch
4. Memory access
5. Register write back
Since all of these steps utilize different parts of the CPU, it is possible to apply instruction pipelining, a technique for implementing instruction-level parallelism within a single processor. Additionally, a pipelined computer usually has "pipeline registers" after each stage. They store information about the instructions and calculations so that the logic gates of the next stage are able to do the next step.
And the more pipeline stages there are, the faster the pipeline is as each stage becomes shorter. Ideally, a processor with a five staged pipeline should be five times faster than a non-pipelined processor. Pipelining can be further sped up by introducing more steps (Superpipelining) or using multiple pipelines in parallel(Superscalar pipelining).