Answer to Question #176935 in Algorithms for Tisha

Question

On the MIPS architecture, for example, the load-linked and store-conditional instructions can be

used in tandem to build locks and other concurrent structures. The C pseudocode for these

instructions is shown below. Alpha, PowerPC, and ARM provide similar instructions.

// Actions of thread Ti

1: int LoadLinked(int *ptr) {

2: return *ptr;

3: }

4: int StoreConditional(int *ptr, int value) {

5: if (no other thread has updated *ptr since the last LoadLinked access to *ptr by thread Ti)

6: {

7: *ptr = value;

8: return 1; // success

9: }

10: else {

11: return 0; // failed to update

12: }

13: }

The key difference comes with the store-conditional, which only

succeeds (and updates the value stored at the address just load-linked from) if no intervening store

by another thread to the address has taken place. In the case of success, the store-conditional returns

1 and updates the value at ptr to value; if it fails, the value at ptr is not updated and 0 is returned.

Please develop a mutex lock using this instruction.

Answer 1

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