# Answer to Question #56777 in Other Engineering for DJKovesh

Question #56777

Derive a minimal state table for an FSM that acts as a three-bit parity generator. For every three bits that are observed on the input w during three consecutive clock cycles, the FSM generates the parity bit p = 1 if and only if the number of 1s in the three-bit sequence is odd.

Expert's answer

## Comments

## Leave a comment