Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a
clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds.
Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
(A) I only (B) II only (C) I and III only (D) II and III only (E) I, II, and III