Answer to Question #22880 in Other Engineering for Sujata Roy

Question #22880
A computer is taking 5 clock cycles if data is present in the cache memory. In all instructions only 30% data are fetched, but miss rate is 10% and CPU gives miss penalty of 10 clock cycles for this. What will be the gain if all instructions fetched are available in the cache memory? (a) 5.2 (b) 6.3 (c) 1.79 (d) None of these
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