Answer to Question #62529 in Electrical Engineering for soon later

Question

For the unsigned addition of the given bit-pattern pair, identify the overall delay (i.e. the delay at which all the outputs of the circuit are finalized) experienced in the case of each unsigned adder circuit mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in.
0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0
1 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1
i. RCA
ii. CCA
iii. BCLA with block size=8
iv. RCA-BCL adder with block size=8
v. CSA with block size=2
vi. CSelA with block size=8. Assume that the first block is implemented as an RCA