Answer to Question #242878 in Electrical Engineering for aijaz

Question

A common bus system which is capable of transferring 4 bits at time with number of registers are 4 each register is of 4 bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register.

please also show diagram and truth table

Answer 1

The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.

The selection lines choose the four bits of one register and transfer them into the four-line

common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four

multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes the

bus lines to receive the content of register A since the outputs of this register are connected to the

0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content

provided by register B.

The following function table shows the register that is selected by the bus for each of the four

possible binary values of the Selection lines