Answer to Question #242633 in Electrical Engineering for pawan

Question

A common bus system which is capable of transferring 2 bits at time with number of

registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many

multiplexers are required and what will be the size of multiplexer with truth table Also explain

how to gather data from this bus back into register

Answer 1

The input logic circuit in diagrammatic representation has three inputs, I0, I1, and T, and three outputs, S0, S1 and L. variables S0 and S1 select one of the source addresses for CAR. Variable L enables the load input in SBR. The binary values of the two selection variables determine the path in the multiplexer. For example, with S1 S0 = 10, multiplexer input number 2 is selected and establishes a transfer. The truth table is shown below: