Question #242169

Each Question carries 10 Marks

Q1. Design a Shift register which performs:

i) Parallel load function, when input 00 will be applied in S1S0 respectively.

ii) Shift up function, when input 01 will be applied in S1S0 respectively.

iii) Shift down function, when input 10 will be applied in S1S0 respectively.

iv) No change function, when input 11 will be applied in S1S0 respectively.

Q2. An 8 bit register contains the binary value 10011100.What is the register value after an arithmetic shift right? Starting from the initial number 10011100, determine the register value after an arithmetic shift left and state whether there is an overflow or not?

Q2 Design a 3-bit arithmetic unit which performs seven distinct operations. Also explain its working by taking a suitable example. Draw truth table showing the inputs and corresponding operation of arithmetic unit.

Q1. Design a Shift register which performs:

i) Parallel load function, when input 00 will be applied in S1S0 respectively.

ii) Shift up function, when input 01 will be applied in S1S0 respectively.

iii) Shift down function, when input 10 will be applied in S1S0 respectively.

iv) No change function, when input 11 will be applied in S1S0 respectively.

Q2. An 8 bit register contains the binary value 10011100.What is the register value after an arithmetic shift right? Starting from the initial number 10011100, determine the register value after an arithmetic shift left and state whether there is an overflow or not?

Q2 Design a 3-bit arithmetic unit which performs seven distinct operations. Also explain its working by taking a suitable example. Draw truth table showing the inputs and corresponding operation of arithmetic unit.

Expert's answer

When the third clock pulse arrives this logic “1” value moves to the output of FFC ( Q_{C} ) and so on until the arrival of the fifth clock pulse which sets all the outputs Q_{A} to Q_{D} back again to logic level “0” because the input to FFA has remained constant at logic level “0”.

The effect of each clock pulse is to shift the data contents of each stage one place to the right, and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register. This data value can now be read directly from the outputs of Q_{A} to Q_{D}.

Then the data has been converted from a serial data input signal to a parallel data output. The truth table and following waveforms show the propagation of the logic “1” through the register from left to right as shown.

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