Show the hardware that implements the following statement. Include the logic gates for the control function and a block diagram for the binary counter with a count enable input.
xyT0 + T1 + y’ T2: AR ç AR
Given the left "side" of the image is trivial. Information is loaded from a bus to AR known as “ address register”
when the output of the organize logic is 1.
AR is incremented “INR” at the next rising of the clock signal.
This information is the passed on the AR which has clear “CLR” and load “LD” inputs as well.