Question #240511

The outputs of four registers, A, B, C, D, H, L are connected through 8:1 line

multiplexer to the input of a fifth register, X. Each register is 16 bits long. The

required transfers are dictated by four timing variables, T0 through T3 as follows:

T0 : X←A

T1 : X←B

T2 : X←C

T3 : X←D

The timing variables are mutually exclusive, which means that only one variable is

equal to 1 at any given time, while the others are equal to 0. Draw a block diagram

showing the hardware implementation of the register transfers. Include the

connections necessary from the four timing variables to the selection inputs of the

multiplexers and to the load input of register X

multiplexer to the input of a fifth register, X. Each register is 16 bits long. The

required transfers are dictated by four timing variables, T0 through T3 as follows:

T0 : X←A

T1 : X←B

T2 : X←C

T3 : X←D

The timing variables are mutually exclusive, which means that only one variable is

equal to 1 at any given time, while the others are equal to 0. Draw a block diagram

showing the hardware implementation of the register transfers. Include the

connections necessary from the four timing variables to the selection inputs of the

multiplexers and to the load input of register X

Expert's answer

The truth table for the outputs:

Use the “sum of product” technique to get the logic expressions for the selection lines

and the load signal:

"S1 = T2 + T3\\\\\n\nS0 = T1 + T3\\\\\n\nLoad = T0 + T1 + T2 + T3"

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