Deaign a bus system that can support 4 registors of 2 bits each . Explain why you created the bus in this method. Also explain how to gather data from this bus back into register
A bus is made up of a series of common lines, one for each bit of a register, via which binary data is transmitted one bit at a time. During a register transfer, the bus selects which register to use based on control signals.
A Bus system for four registers is depicted in the block diagram below. It is built of four 4 * 1 Multiplexers, each with four data inputs (0 through 3) and two selection inputs (S1 and S2).
Labels have been provided to make it easier for you to comprehend the input-output configuration of a Bus system with four registers. For example, register A's output 1 is linked to MUX1's input 0.
S1 and S2 are the two selection lines that link to the selection inputs of all four multiplexers. The selection lines choose four bits from a register and send them to the four-line common bus.
When both select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four multiplexers are picked and applied to the bus outputs. Because the outputs of this register are linked to the 0 data inputs of the multiplexers, the bus lines get the content of register A.
Similarly, when S1S0 = 01, register B is chosen, and the bus lines get the material from register B.
The function table below illustrates which register is picked by the bus for each of the four binary values of the Selection lines.