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# Answer to Question #178360 in Electrical Engineering for I. Bhat

Question #178360

A si pn junction ( Na= 1016 cm-4 and Nd = 4 × 10 16 cm-3) is biased with Va= -3v . Calculate the built-in potential and depletion layer width ?

1
2021-04-12T01:55:13-0400

"Given silicon pn-junction at T= 300K, doped at Nd = 1016 and Na = 1017 and cj = 0.8pF, VR=5v\n\nSolution\n\nCarrier concentration of silicon at T= 300K is nt = 1.5*1010 cm-3\n\nPotential barrier of pn junction is\n\nVbi = (kT\/e) ln (NaNd\/n2i) = VTln(NaNd\/n2i)\n\n= (0.026) ln (1016*1017\/(1.5*1010)2)\n\n= 0.757V\n\nJunction capacitance\n\nCj= Cjo (1+VR\/Vbi)-1\/2\n\nwhere Cjo is junction\n\n0.8*10-12 = (Cjo) ( 1 +5\/0.757)-1\/2\n\n0.8*10-12 = (Cjo) (0.3626)\n\nCjo = 2.21pF\n\nTherefore the zero biased junction capacitance at VR = 5V is 2.21pF"

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